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1 of 53 january 19, 2006 ? 2005 integrated device technology, inc. dsc 6214 idt and the idt logo are trademarks of integrated device technology, inc. device overview device overview device overview device overview the 79rc32435 is a member of the idt? interprise? family of pci integrated communications processors. it incorporates a high perfor- mance cpu core and a number of on-chip peripherals. the integrated processor is designed to transfer information from i/o modules to main memory with minimal cpu intervention, using a highly sophisticated direct memory access (dma) engine. all data transfers through the rc32435 are achieved by writing data from an on-chip i/o peripheral to main memory and then out to another i/o module. features features features features 32-bit cpu core ? mips32 instruction set ? cache sizes: 8kb instruction and data caches, 4-way set associative, cache line locking, non-blocking prefetches ? 16 dual-entry jtlb with variable page sizes ? 3-entry instruction tlb ? 3-entry data tlb ? max issue rate of one 32x16 multiply per clock ? max issue rate of one 32x32 multiply every other clock ? cpu control with start, stop, and single stepping ? software breakpoints support ? hardware breakpoints on virtual addresses ? ice interface that is compatible with v2.5 of the ejtag spec- ification pci interface ? 32-bit pci revision 2.2 compliant ? supports host or satellite operation in both master and target modes ? support for synchronous and asynchronous operation ? pci clock supports frequencies from 16 mhz to 66 mhz ? pci arbiter in host mode: supports 6 external masters, fixed priority or round robin arbitration ?i 2 o ?like? pci messaging unit ethernet interface ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? supports mii or rmii phy interface ? supports 64 entry hash table based multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x- 1997 ddr memory controller ? supports up to 256mb of ddr sdram ? 1 chip select supporting 4 internal ddr banks ? supports a 16-bit wide data port using x8 or x16 bit wide ddr sdram devices ? supports 64 mb, 128 mb, 256 mb, 512 mb, and 1gb ddr sdram devices ? data bus multiplexing support allows interfacing to standard ddr dimms and sodimms ? automatic refresh generation b b b block diagram lock diagram lock diagram lock diagram ejtag mmu d. cache i. cache mips-32 cpu core ice interrupt controller 3 counter timers dma controller arbiter ddr 1 uart (16550) gpio interface pci master/target memory & peripheral bus (8-bit) serial channel gpio pins pci bus controller spi spi bus : : 10/100 1 ethernet interface mii/rmii ipbus tm interface pci arbiter (host mode) pmbus ddr controllers (16-bit) memory & i/o controller bus/system integrity monitor nvram controller i 2 c controller i 2 c bus 79rc32435 idt tm interprise tm integrated communications processor
2 of 53 january 19, 2006 idt 79rc32435 non-volatile ram ? provides 512-bits of non-volatile storage ? eliminates need for external boot configuration vector ? stores initial pci configuration register values when pci configured to operate in satellite mode with suspended cpu execution ? authorization unit ensures only authorized software will operate on the system memory and peripheral device controller ? provides ?glueless? interface to standard sram, flash, rom, dual-port memory, and peripheral devices ? demultiplexed address and data buses: 8-bit data bus, 26-bit address bus, 4 chip selects, control for external data bus buffers automatic byte gathering and scattering ? flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/post- write delay (0 to 31), supports external wait state generation, supports intel and motorola style peripherals ? write protect capability per chip select ? programmable bus transaction timer generates warm reset when counter expires ? supports up to 64 mb of memory per chip select dma controller ? 6 dma channels: two channels for pci (pci to memory and memory to pci), two channels for the ethernet interface, and two channels for memory to memory dma operations ? provides flexible descriptor based operation ? supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length universal asynchronous receiver transmitter (uart) ? compatible with the 16550 and 16450 uarts ? 16-byte transmit and receive buffers ? programmable baud rate generator derived from the system clock ? fully programmable serial characteristics: ? 5, 6, 7, or 8 bit characters ? even, odd or no parity bit generation and detection ? 1, 1-1/2 or 2 stop bit generation ? line break generation and detection ? false start bit detection ? internal loopback mode i 2 c-bus ? supports standard 100 kbps mode as well as 400 kbps fast mode ? supports 7-bit and 10-bit addressing ? supports four modes: master transmitter, master receiver, slave transmitter, slave receiver additional general purpose peripherals ? interrupt controller ? system integrity functions ? general purpose i/o controller ? serial peripheral interface (spi) counter/timers ? three general purpose 32-bit counter timers ? timers may be cascaded ? selectable counter/timer clock source jtag interface ? compatible with ieee std. 1149.1 - 1990 c c c cpu execution cor pu execution cor pu execution cor pu execution core e e e the 32-bit cpu core is 100% compatible with the mips32 instruction set architecture (isa). specifically, this device features the 4kc cpu core developed by mips technologies inc. (www.mips.com). this core issues a single instruction per cycle, includes a five stage pipeline and is optimized for applications that require integer arithmetic. the cpu core includes 8 kb instruction and 8 kb data caches. both caches are 4-way set associative and can be locked on a per line basis, which allows the programmer control over this precious on-chip memory resource. the core also features a memory management unit (mmu). the cpu core also incorporates an enhanced joint test access group (ejtag) interface that is used to interface to in-circuit emulator tools, providing access to internal registers and enabling the part to be controlled externally, simplifying the system debug process. the use of this core allows idt's customers to leverage the broad range of software and development tools available for the mips archi- tecture, including operating systems, compilers, and in-circuit emula- tors. pci interface pci interface pci interface pci interface the pci interface on the rc32435 is compatible with version 2.2 of the pci specification. an on-chip arbiter supports up to six external bus masters, supporting both fixed priority and rotating priority arbitration schemes. the part can support both satellite and host pci configura- tions, enabling the rc32435 to act as a slave controller for a pci add-in card application or as the primary pci controller in the system. the pci interface can be operated synchronously or asynchronously to the other i/o interfaces on the rc32435 device. ethernet interface ethernet interface ethernet interface ethernet interface the rc32435 has one ethernet channel supporting 10mbps and 100mbps speeds to provide a standard media independent interface (mii or rmii), allowing a wide range of external devices to be connected efficiently. double data rate memory controller double data rate memory controller double data rate memory controller double data rate memory controller the rc32435 incorporates a high performance double data rate (ddr) memory controller which supports x16 memory configurations up to 256mb. this module provides all of the signals required to interface to discrete memory devices, including a chip select, differential clocking outputs and data strobes.
3 of 53 january 19, 2006 idt 79rc32435 m m m memory and i emory and i emory and i emory and i/ / / /o controlle o controlle o controlle o controller r r r the rc32435 uses a dedicated local memory/io controller including a de-multiplexed 8-bit data and 26-bit address bus. it includes all of the signals required to interface directly to a maximum of four intel or motorola-style external peripherals. dma controller dma controller dma controller dma controller the dma controller consists of 6 independent dma channels, all of which operate in exactly the same manner. the dma controller off-loads the cpu core from moving data among the on-chip interfaces, external peripherals, and memory. the controller supports scatter/gather dma with no alignment restrictions, making it appropriate for communications and graphics systems. u u u uart interface art interface art interface art interface the rc32435 contains a serial channel (uart) that is compatible with the industry standard 16550 uart. i i i i 2 2 2 2 c interface c interface c interface c interface the standard i2c interface allows the rc32435 to connect to a number of standard external peripherals for a more complete system solution. the rc32435 supports both master and slave operations. general purpose i/o controller general purpose i/o controller general purpose i/o controller general purpose i/o controller the rc32435 has 14 general purpose input/output pins. each pin may be used as an active high or active low level interrupt or non- maskable interrupt input, and each signal may be used as a bit input or output port. system integrity functions system integrity functions system integrity functions system integrity functions the rc32435 contains a programmable watchdog timer that gener- ates a non-maskable interrupt (nmi) when the counter expires and also contains an address space monitor that reports errors in response to accesses to undecoded address regions. t t t thermal considerations hermal considerations hermal considerations hermal considerations the rc32435 is guaranteed in an ambient temperature range of 0 to +70 c for commercial temperature devices and - 40 to +85 for industrial temperature devices. revision histor revision histor revision histor revision history y y y january 19, 2006 : initial publication.
4 of 53 january 19, 2006 idt 79rc32435 p p p pin description table in description table in description table in description table the following table lists the functions of the pins provided on the rc32435. some of the functions listed may be multiplexed on to the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, wh en at a logic one (high) level. signal type name/description memory and peripheral bus bdirn o external buffer direction. controls the direction of the external data bus buffer for the memory and peripheral bus. if the rc32435 memory and peripheral bus is connected to the a side of a transceiver, such as an idt74fct245, then this pin may be directly connected to the direction control (e.g., bdir) pin of the transceiver. boen o external buffer enable. this signal provides an output enable control for an external buffer on the memory and peripheral data bus. wen o write enables. this signal is the memory and peripheral bus write enable sig- nal. csn[3:0] o chip selects. these signals are used to select an external device on the mem- ory and peripheral bus. maddr[21:0] o address bus. 22-bit memory and peripheral bus address bus. maddr[25:22] are available as gpio alternate functions. mdata[7:0] i/o data bus. 8-bit memory and peripheral data bus. during a cold reset, these pins function as inputs that are used to load the boot configuration vector. oen o output enable. this signal is asserted when data should be driven by an exter- nal device on the memory and peripheral bus. rwn o read write. this signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction. a high level indicates a read from an external device. a low level indicates a write to an external device. waitackn i wait or transfer acknowledge. when configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. when configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. ddr bus ddraddr[13:0] o ddr address bus. 14-bit multiplexed ddr address bus. this bus is used to transfer the addresses to the ddr devices. ddrba[1:0] o ddr bank address. these signals are used to transfer the bank address to the ddrs. ddrcasn o ddr column address strobe. this signal is asserted during ddr transac- tions. ddrcke o ddr clock enable. the ddr clock enable signal is asserted during normal ddr operation. this signal is negated following a cold reset or during a power down operation. ddrckn o ddr negative ddr clock. this signal is the negative clock of the differential ddr clock pair. table 1 pin description (part 1 of 6)
5 of 53 january 19, 2006 idt 79rc32435 ddrckp o ddr positive ddr clock. this signal is the positive clock of the differential ddr clock pair. ddrcsn o ddr chip selects. this active low signal is used to select ddr device(s) on the ddr bus. ddrdata[15:0] i/o ddr data bus. 16-bit ddr data bus is used to transfer data between the rc32435 and the ddr devices. data is transferred on both edges of the clock. ddrdm[1:0] o ddr data write enables. byte data write enables are used to enable specific byte lanes during ddr writes. ddrdm[0] corresponds to ddrdata[7:0] ddrdm[1] corresponds to ddrdata[15:8] ddrdqs[1:0] i/o ddr data strobes. ddr byte data strobes are used to clock data between ddr devices and the rc32435. these strobes are inputs during ddr reads and outputs during ddr writes. ddrdqs[0] corresponds to ddrdata[7:0] ddrdqs[1] corresponds to ddrdata[15:8] ddrrasn o ddr row address strobe. the ddr row address strobe is asserted during ddr transactions. ddrvref i ddr voltage reference. sstl_2 ddr voltage reference is generated by an external source. ddrwen o ddr write enable. ddr write enable is asserted during ddr write transac- tions. pci bus pciad[31:0] i/o pci multiplexed address/data bus . address is driven by a bus master during initial pciframen assertion. data is then driven by the bus master during writes or by the bus target during reads. pcicben[3:0] i/o pci multiplexed command/byte enable bus . pci commands are driven by the bus master during the initial pciframen assertion. byte enable signals are driven by the bus master during subsequent data phase(s). pciclk i pci clock . clock used for all pci bus transactions. pcidevseln i/o pci device select . this signal is driven by a bus target to indicate that the tar- get has decoded the address as one of its own address spaces. pciframen i/o pci frame . driven by a bus master. assertion indicates the beginning of a bus transaction. negation indicates the last data. pcigntn[3:0] i/o pci bus grant . in pci host mode with internal arbiter: the assertion of these signals indicates to the agent that the internal rc32435 arbiter has granted the agent access to the pci bus. in pci host mode with external arbiter: pcigntn[0]: asserted by an external arbiter to indicate to the rc32435 that access to the pci bus has been granted. pcigntn[3:1]: unused and driven high. in pci satellite mode: pcigntn[0]: this signal is asserted by an external arbiter to indicate to the rc32435 that access to the pci bus has been granted. pcigntn[3:1]: unused and driven high. pciirdyn i/o pci initiator ready . driven by the bus master to indicate that the current datum can complete. signal type name/description table 1 pin description (part 2 of 6)
6 of 53 january 19, 2006 idt 79rc32435 pcilockn i/o pci lock . this signal is asserted by an external bus master to indicate that an exclusive operation is occurring. pcipar i/o pci parity . even parity of the pciad[31:0] bus. driven by the bus master during address and write data phases. driven by the bus target during the read data phase. pciperrn i/o pci parity error . if a parity error is detected, this signal is asserted by the receiving bus agent 2 clocks after the data is received. pcireqn[3:0] i/o pci bus request. in pci host mode with internal arbiter: these signals are inputs whose assertion indicates to the internal rc32435 arbiter that an agent desires ownership of the pci bus. in pci host mode with external arbiter: pcireqn[0]: asserted by the rc32435 to request ownership of the pci bus. pcireqn[3:1]: unused and driven high. in pci satellite mode: pcireqn[0]: this signal is asserted by the rc32435 to request use of the pci bus. pcireqn[1]: function changes to pciidsel and is used as a chip select during configuration read and write transactions. pcireqn[3:2]: unused and driven high. pcirstn i/o pci reset . in host mode, this signal is asserted by the rc32435 to generate a pci reset. in satellite mode, assertion of this signal initiates a warm reset. pciserrn i/o pci system error . this signal is driven by an agent to indicate an address par- ity error, data parity error during a special cycle command, or any other system error. requires an external pull-up. pcistopn i/o pci stop . driven by the bus target to terminate the current bus transaction. for example, to indicate a retry. pcitrdyn i/o pci target ready . driven by the bus target to indicate that the current data can complete. general purpose input/output gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sout alternate function: uart channel 0 serial output. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sinp alternate function: uart channel 0 serial input. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0rtsn alternate function: uart channel 0 request to send. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0ctsn alternate function: uart channel 0 clear to send. signal type name/description table 1 pin description (part 3 of 6)
7 of 53 january 19, 2006 idt 79rc32435 gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[22] alternate function: memory and peripheral bus address. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[23] alternate function: memory and peripheral bus address. gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[24] alternate function: memory and peripheral bus address. the value of this pin may be used as a counter timer clock input (see counter timer clock select register in chapter 14, counter/timers, of the rc32435 user manual). gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[25] alternate function: memory and peripheral bus address. the value of this pin may be used as a counter timer clock input (see counter timer clock select register in chapter 14, counter/timers, of the rc32435 user manual). gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: cpu alternate function: cpu or dma debug output pin. gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[4] alternate function: pci request 4. gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[4] alternate function: pci grant 4. gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[5] alternate function: pci request 5. gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[5] alternate function: pci grant 5. gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcimuintn alternate function: pci messaging unit interrupt output. spi interface sck i/o serial clock . this signal is used as the serial clock output. this pin may be used as a bit input/output port. signal type name/description table 1 pin description (part 4 of 6)
8 of 53 january 19, 2006 idt 79rc32435 sdi i/o serial data input . this signal is used to shift in serial data. this pin may be used as a bit input/output port. sdo i/o serial data output . this signal is used shift out serial data. i 2 c bus interface scl i/o i 2 c clock. i 2 c-bus clock. sda i/o i 2 c data bus. i 2 c-bus data bus. ethernet interfaces miicl i ethernet mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. miicrs i ethernet mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. miirxclk i ethernet mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. this pin also functions as the rmii ref_clk input. miirxd[3:0] i ethernet mii receive data. this nibble wide data bus contains the data received by the ethernet phy. this pin also functions as the rmii rxd[1:0] input. miirxdv i ethernet mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. this pin also functions as the rmii crs_dv input. miirxer i ethernet mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. this pin also functions as the rmii rx_er input. miitxclk i ethernet mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. miitxd[3:0] o ethernet mii transmit data. this nibble wide data bus contains the data to be transmitted. this pin also functions as the rmii txd[1:0] output. miitxenp o ethernet mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. this pin also functions as the rmii tx_en output. miitxer o ethernet mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. miimdc o mii management data clock. this signal is used as a timing reference for transmission of data on the management interface. miimdio i/o mii management data. this bidirectional signal is used to transfer data between the station management entity and the ethernet phy. ejtag / jtag jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. when using the ejtag debug inter- face, this pin should be left disconnected (since there is an internal pull-up) or driven high. signal type name/description table 1 pin description (part 5 of 6)
9 of 53 january 19, 2006 idt 79rc32435 ejtag_tms i ejtag mode . the value on this signal controls the test mode select of the ejtag controller. when using the jtag boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic, jtag tap controller, and the ejtag debug tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in func- tional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock jtag_tck while holding ejtag_tms and/or jtag_tms high. jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic, jtag controller, or the ejtag controller. jtag_tck is independent of the system and the processor clock with a nomi- nal 50% duty cycle. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic, jtag controller, or the ejtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic, jtag controller, or the ejtag controller. system clk i master clock. this is the master clock input. the processor frequency is a mul- tiple of this clock frequency. this clock is used as the system clock for all mem- ory and peripheral bus operations. extbcv i load external boot configuration vector. when this pin is asserted (i.e., high) the boot configuration vector is loaded from an externally supplied value during a cold reset. when this pin is negated, the boot configuration vector is taken from the nvram located on-chip. extclk o external clock. this clock is used for all memory and peripheral bus opera- tions. coldrstn i cold reset. the assertion of this signal initiates a cold reset. this causes the processor state to be initialized, boot configuration to be loaded, and the internal pll to lock onto the master clock (clk). rstn i/o reset. the assertion of this bidirectional signal initiates a warm reset. this sig- nal is asserted by the rc32435 during a warm reset. signal type name/description table 1 pin description (part 6 of 6)
10 of 53 january 19, 2006 idt 79rc32435 pin characteristics pin characteristics pin characteristics pin characteristics note: some input pads of the rc32435 do not contain internal pull-ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially critical for unused control signal inputs (such as waitackn) which, if left floating, could adversel y affect the rc32435?s operation. also, any input pin left floating can cause a slight increase in power consumption. function pin name type buffer i/o type internal resistor notes 1 memory and peripheral bus bdirn o lvttl high drive boen o lvttl high drive wen o lvttl high drive csn[3:0] o lvttl high drive maddr[21:0] i/o lvttl high drive mdata[7:0] i/o lvttl high drive oen o lvttl high drive rwn o lvttl high drive waitackn i lvttl sti pull-up ddr bus ddraddr[13:0] o sstl_2 ddrba[1:0] o sstl_2 ddrcasn o sstl_2 ddrcke o sstl_2 / lvc- mos ddrckn o sstl_2 ddrckp o sstl_2 ddrcsn o sstl_2 ddrdata[15:0] i/o sstl_2 ddrdm[1:0] o sstl_2 ddrdqs[1:0] i/o sstl_2 ddrrasn o sstl_2 ddrvref i analog ddrwen o sstl_2 pci bus interface pciad[31:0] i/o pci pcicben[3:0] i/o pci pciclk i pci pcidevseln i/o pci pull-up on board pciframen i/o pci pull-up on board pcigntn[3:0] i/o pci pull-up on board pciirdyn i/o pci pull-up on board pcilockn i/o pci pcipar i/o pci pciperrn i/o pci pcireqn[3:0] i/o pci pull-up on board pcirstn i/o pci pull-down on board pciserrn i/o pci open collector pull-up on board pcistopn i/o pci pull-up on board pcitrdyn i/o pci pull-up on board general purpose i/o gpio[8:0] i/o lvttl high drive pull-up gpio[13:9] i/o pci pull-up on board table 2 pin characteristics (part 1 of 2)
11 of 53 january 19, 2006 idt 79rc32435 serial peripheral interface sck i/o lvttl high drive pull-up pull-up on board sdi i/o lvttl high drive pull-up pull-up on board sdo i/o lvttl high drive pull-up pull-up on board i 2 c-bus interface scl i/o lvttl low drive/sti pull-up on board 2 sda i/o lvttl low drive/sti pull-up on board 2 ethernet interfaces miicl i lvttl sti pull-down miicrs i lvttl sti pull-down miirxclk i lvttl sti pull-up miirxd[3:0] i lvttl sti pull-up miirxdv i lvttl sti pull-down miirxer i lvttl sti pull-down miitxclk i lvttl sti pull-up miitxd[3:0] o lvttl low drive miitxenp o lvttl low drive miitxer o lvttl low drive miimdc o lvttl low drive miimdio i/o lvttl low drive pull-up ejtag / jtag jtag_tms i lvttl sti pull-up ejtag_tms i lvttl sti pull-up jtag_trst_n i lvttl sti pull-up jtag_tck i lvttl sti pull-up jtag_tdo o lvttl low drive jtag_tdi i lvttl sti pull-up system clk i lvttl sti extbcv i lvttl sti pull-down extclk o lvttl high drive coldrstn i lvttl sti rstn i/o lvttl low drive / sti pull-up pull-up on board 1. external pull-up required in most system applications. some applications may require additional pull-ups not identified in this table. 2. use a 2.2k pull-up resistor for i2c pins. function pin name type buffer i/o type internal resistor notes 1 table 2 pin characteristics (part 2 of 2)
12 of 53 january 19, 2006 idt 79rc32435 boot configuration vector boot configuration vector boot configuration vector boot configuration vector the encoding of the boot configuration vector is described in table 3, and the vector input is illustrated in figure 4. the val ue of the boot configura- tion vector read in by the rc32435 during a cold reset may be determined by reading the boot configuration vector (bcv) registe r. signal name/description maddr[3:0] cpu pipeline clock multiplier . this field specifies the value by which the pll multi- plies the master clock input (clk) to obtain the processor clock frequency (pclk). for master clock input frequency constraints, refer to table 3.2 in the rc32435 user man- ual. 0x0 - pll bypass 0x1 - multiply by 3 0x2 - multiply by 4 0x3 - multiply by 5 - reserved 0x4 - multiply by 5 0x5 - multiply by 6 - reserved 0x6 - multiply by 6 0x7 - multiply by 8 0x8 - multiply by 10 0x9 through 0xf - reserved maddr[5:4] external clock divider . this field specifies the value by which the ipbus clock (iclk), which is always 1/2 pclk, is divided in order to generate the external clock output on the extclk pin. 0x0 - divide by 1 0x1 - divide by 2 0x2 - divide by 4 0x3 - reserved maddr[6] endian. this bit specifies the endianness. 0x0 - little endian 0x1 - big endian maddr[7] reset mode . this bit specifies the length of time the rstn signal is driven. 0x0 - normal reset: rstn driven for minimum of 4000 clock cycles. if the internal boot configuration vector is selected, the expiration of an 18-bit counter operating at the master clock input (clk) frequency is used as the pll stabilization delay. 0x1 - reserved maddr[10:8] pci mode . this bit controls the operating mode of the pci bus interface. the initial value of the en bit in the pcic register is determined by the pci mode. 0x0 - disabled (en initial value is zero) 0x1 - pci satellite mode with pci target not ready (en initial value is one) 0x2 - pci satellite mode with suspended cpu execution (en initial value is one) 0x3 - pci host mode with external arbiter (en initial value is zero) 0x4 - pci host mode with internal arbiter using fixed priority arbitration algorithm (en initial value is zero) 0x5 - pci host mode with internal arbiter using round robin arbitration algorithm (en initial value is zero) 0x6 - reserved 0x7 - reserved table 3 boot configuration encoding (part 1 of 2)
13 of 53 january 19, 2006 idt 79rc32435 maddr[11] disable watchdog timer . when this bit is set, the watchdog timer is disabled follow- ing a cold reset. 0x0 - watchdog timer enabled 0x1 - watchdog timer disabled maddr[13:12] reserved . these pins must be driven low during boot configuration. maddr[15:14] reserved . must be set to zero. signal name/description table 3 boot configuration encoding (part 2 of 2)
14 of 53 january 19, 2006 idt 79rc32435 l l l logic diagram ? ogic diagram ? ogic diagram ? ogic diagram ? rc rc rc rc32435 32435 32435 32435 figure 1 logic diagram system signals memory and peripheral bus clk coldrstn rstn 4 miimdc miimdio miicl miicrs miirxclk miirxd[3:0] miirxdv miirxer miitxclk miitxd[3:0] miitxenp miitxer bdirn boen wen csn[3:0] maddr[21:0] mdata[7:0] oen rwn waitackn ddraddr[13:0] ddrba[1:0] ddrcasn ddrcke ddrckn ddrckp ddrcsn ddrdata[15:0] ddrdm[1:0] ddrdqs[1:0] ddrrasn ddrvref ddrwen pciad[31:0] pcicben[3:0] pciclk pcidevseln pciframen pcigntn[3:0] pciirdyn pcilockn pcipar pciperrn pcireqn[3:0] pcirstn pciserrn pcistopn pcitrdyn gpio[13:0] sdo jtag_tck jtag_tdi jtag_tdo jtag_tms jtag_trst_n 4 14 4 4 4 32 2 2 16 2 14 8 22 4 ejtag / jtag signals general purpose i/o spi pci bus ddr bus ethernet rc32435 vcccore vcci/o vss vccpll vsspll power/ground sdi sck ejtag_tms extclk extbcv sda scl i 2 c-bus
15 of 53 january 19, 2006 idt 79rc32435 ac timing definitions ac timing definitions ac timing definitions ac timing definitions below are examples of the ac timing characteristics used throughout this document. figure 2 ac timing definitions waveform symbol definition tper clock period. tlow clock low. amount of time the clock is low in one clock period. thigh clock high. amount of time the clock is high in one clock period. trise rise time. low to high transition time. tfall fall time. high to low transition time. tjitter jitter. amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. tdo data out. amount of time after the reference clock edge that the output will become valid. the minimum time represents the d ata output hold. the maximum time represents the earliest time the designer can use the data. tzd z state to data valid. amount of time after the reference clock edge that the tri-stated output takes to become valid. tdz data valid to z state. amount of time after the reference clock edge that the valid output takes to become tri-stated. tsu input set-up. amount of time before the reference clock edge that the input must be valid. thld input hold. amount of time after the reference clock edge that the input must remain valid. tpw pulse width. amount of time the input or output is active for asynchronous signals. tslew slew rate. the rise or fall rate for a signal to go from a high to low, or low to high. x(clock) timing value. this notation represents a value of ?x? multiplied by the clock time period of the specified clock. using 5(clk) as an example: x = 5 and the oscillator clock (clk) = 25mhz, then the timing value is 200. tskew skew. the amount of time two signal edges deviate from one another. table 4 ac timing definitions tdz tzd tdo tpw tpw thld tsu tlow thigh thigh tper clock output signal 1 output signal 2 input signal 1 signal 1 tjitter trise tfall tdo signal 2 signal 3 tskew
16 of 53 january 19, 2006 idt 79rc32435 s s s system clock parameters ystem clock parameters ystem clock parameters ystem clock parameters (values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 15 and 16.) figure 3 clock parameters waveform parameter symbol reference edge 266mhz 300mhz 350mhz 400mhz units timing diagram reference min max min max min max min max pclk 1 1. the cpu pipeline clock (pclk) speed is selected during cold reset by the boot configuration vector (see table 3). refer to chap ter 3, clocking and initialization, in the rc32435 user reference manual for the allowable frequency ranges of clk and pclk. frequency none 200 266 200 300 200 350 200 400 mhz see figure 3. tper 3.8 5.0 3.3 5.0 2.85 5.0 2.5 5.0 ns iclk 2,3,4 2. iclk is the internal ipbus clock. it is always equal to pclk divided by 2. this clock cannot be sampled externally. 3. the ethernet clock (miixrxclk and miixtxclk) frequency must be equal to or less than 1/2 iclk (miixrxclk and miixtxclk <= 1/2(i clk)). 4. pciclk must be equal to or less than two times iclk (pciclk <= 2(iclk)) with a maximum pciclk of 66 mhz. frequency none 100 133 100 150 100 175 100 200 mhz tper 7.5 10.0 6.7 10.0 5.7 10.0 5.0 10.0 ns clk 5 5. the input clock (clk) is input from the external oscillator to the internal pll. frequency none 25 125 25 125 25 125 25 125 mhz tper_5a 8.0 40.0 8.0 40.0 8.0 40.0 8.0 40.0 ns thigh_5a, tlow_5a 40 60 40 60 40 60 40 60 % of tper_5a trise_5a, tfall_5a ? 3.0 ? 3.0 ? 3.0 ? 3.0 ns tjitter_5a ? 0.1 ? 0.1 ? 0.1 ? 0.1 ns table 5 clock parameters tlow_5a thigh_5a tper_5a clk trise_5a tfall_5a tjitter_5a tjitter_5a
17 of 53 january 19, 2006 idt 79rc32435 ac timing characteristics ac timing characteristics ac timing characteristics ac timing characteristics (values given below are based on systems running at recommended operating temperatures and supply voltages, shown in tables 15 and 16.) signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max reset coldrstn 1 1. the coldrstn minimum pulse width is the oscillator stabilization time (osc) with v cc stable. tpw_6a 2 2. the values for this symbol were determined by calculation, not by testing. none osc ? osc ? osc ? osc ? ms cold reset see figures 4 and 5. trise_6a none ? 5.0 ? 5.0 ? 5.0 ? 5.0 ns cold reset rstn 3 (input) tpw_6b 2 none 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ?nswarm reset rstn 3 (output) 3. rstn is a bidirectional signal. it is treated as an asynchronous input. tdo_6c coldrstn falling ? 15.0 ? 15.0 ? 15.0 ? 15.0 ns cold reset maddr[15:0] (boot vector) tdz_6d 2 coldrstn falling ? 30.0 ? 30.0 ? 30.0 ? 30.0 ns cold reset tdz_6d 2 rstn falling ? 5(clk) ? 5(clk) ? 5(clk) ? 5(clk) ns warm reset tzd_6d 2 rstn rising 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ? ns warm reset table 6 reset and system ac timing characteristics
18 of 53 january 19, 2006 idt 79rc32435 figure 4 cold reset operation with external boot configuration vector ac timing waveform note: for a diagram showing the cold reset operation with internal boot configuration vector, see figure 3.6 in the rc32435 user reference manual. 1 1. extbcv is asserted (i.e., pulled-up). coldrstn is asserted by external logic. the rc32435 responds by immediately tri-stating the bottom 16-bits of the memory and peripheral address bus (maddr[15:0]), driving the remaining address bus signals (i.e., maddr[21:16]), and asserting rstn. extclk is undefined at this point. 2. external logic drives the boot configuration vector on maddr[15:0]. 3. external logic negates coldrstn and tri-states the boot configuration vector on maddr[15:0]. in response, the rc32435 stops s ampling the boot configuration vector and retains the boot configuration vector value seen two clock cycles earlier (i.e., the value on the maddr[15:0] lines two rising edges of clk earlier). within 16 clk clock cycles after coldrstn is sampled negated, the rc32435 begins drivin g maddr[15:0]. 4. the rc32435 waits for the nvram to initialize (if the disable nvram initialization mode is not selected in the boot configura tion vector) and for the pll to stabilize. 5. the rc32435 then begins generating extclk. 6. after at least 4000 clk clock cycles, the rc32435 tri-states rstn. 7. at least 4000 clk clock cycles after negating rstn, the rc32435 samples rstn. if rstn is negated, cold reset has completed an d the rc32435 cpu begins executing by taking mips reset exception. clk coldrstn rstn maddr[15:0] maddr[21:16] 2 extclk 3 4 5 6 extbcv 4000 clk clock cycles boot configuration vector driven driven * * coldrstn sampled negated (high) by the rc32435 4000 clk clock cycles
19 of 53 january 19, 2006 idt 79rc32435 figure 5 externally initiated warm reset ac timing waveform signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit timing diagram reference min max min max min max min max memory bus - ddr access ddrdata[15:0] tskew_7g ddrdqsx 0 0.9 0 0.8 1 1. meets ddr timing requirements for 150mhz clock rate ddr sdrams with 300 ps remaining margin to compensate for pcb propagation m ismatches, which is adequate to guarantee functional timing, provided the rc32435 ddr layout guidelines are adhered to. 0 0.7 0.0 0.6 ns see figures 6 and 7. tdo_7k 2 2. setup times are calculated as applicable clock period - tdo max. for example, if the ddr is running at 266mhz, it uses a 133mhz input clock. the period for a 133mhz clock is 7.5ns. if the tdo max value is 4.6ns, the t is parameter is 7.5ns minus 4.6ns = 2.9ns. the ddr spec for this parameter is 1ns, so there is 1.9ns of slack left over for board propagation. calculations for t ds are similar, but since this parameter is taken relative to the ddrdqs signals, which are referenced on both edges, the effecti ve period with a 133mhz input clock is only 3.75ns. so, if the max tdo is 1.9ns, we have 3.75ns minus 1.9ns = 1.85ns for t ds . the ddr data sheet specs a value of 0.5ns for 266mhz, so this leaves 1.35ns slack for board propagation delays. 1.2 1.9 1.0 1.7 0.7 1.5 0.5 1.4 ns ddrdm[1:0] tdo_7l ddrdqsx 1.2 1.9 1.0 1.7 0.7 1.5 0.5 1.4 ns ddrdqs[1:0] tdo_7i ddrckp -0.75 0.75 -0.75 0.75 -0.7 0.7 -0.7 0.7 ns ddraddr[13:0], ddrba[1:0], ddrcasn, ddrcke, ddrcsn, ddrrasn, ddrwen tdo_7m ddrckp 1.0 4.0 1.0 4.3 1.0 4.0 1.0 4.0 ns table 7 ddr sdram timing characteristics 1. warm reset condition caused by assertion of rstn by an external agent. 2. the rc32435 tri-states the data bus, mdata[7:0], negates all memory control signals, and itself asserts rstn. the rc32435 con tinues to drive the address bus throughout the entire warm reset. 3. the rc32435 negates rstn after 4000 master clock (clk) clock cycles. 4. external logic negates rstn. 5. the rc32435 samples rstn negated at least 4000 master clock (clk) clock cycles after step 3 and starts driving the data bus, mdata[7:0]. 6. cpu begins executing by taking a mips soft reset exception. the assertion of csn[0] will occur no sooner than 16 clock cycles after the rc32435 samples rstn negated (i.e., step 5). active deasserted active clk coldrstn rstn mdata[7:0] mem control signals ffff_ffff 1 2 4 5 6 3 4000 clk clock cycles 4000 clk clock cycles
20 of 53 january 19, 2006 idt 79rc32435 figure 6 ddr sdram ac timing waveform - sdram read access rowa col a0 col a2 rowb nop actv nop rd rd nop nop prechg nop actv nop bnkx bnkx bnkx bnkx bnkx d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 tdo_7m tdo_7m tdo_7m tdo_7m tskew_7g tskew_7g ddrckp ddrckn ddrcsn ddraddr[13:0] ddrcmd 1 ddrcke ddrba[1:0] ddrdm[1:0] ddrdqsx (ideal) ddrdata[15:0] 2 (ideal) ddrdqsx (min) ddrdata[15:0] 2 ddrdqsx (max) ddrdata[15:0] 2 1 ddrcmd contains ddrrasn, ddrcasn and ddrwen. 2 ddrdata is either 32-bits or 16-bits wide depending on the dbw control bit in ddrc register (see chapter 7, ddr controller, in the rc32435 user reference manual). tac (min) tac (max)
21 of 53 january 19, 2006 idt 79rc32435 figure 7 ddr sdram timing waveform ? write access signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max memory and peripheral bus 1 see figures 8 and 9. maddr[21:0] tdo_8a extclk rising 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5 ns tdz_8a 2 ????????ns tzd_8a 2 ????????ns maddr[25:22] tdo_8b extclk rising 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5 ns tdz_8b 2 ????????ns tzd_8b 2 ????????ns table 8 memory and peripheral bus ac timing characteristics (part 1 of 2) 2 ddrdata is either 32-bits or 16-bits wide depending on the dbw control bit in ddrc register rowa col a0 col a2 nop actv nop wr wr nop nop nop nop nop bnkx bnkx ff dm0 dm1 dm3 ff d0 d1 d2 d3 tdo_7k tdo_7k tdo_7l tdo_7l tdo_7m tdo_7m tdo_7m tdo_7m ddrckp ddrckn ddrcsn ddraddr[13:0] ddrcmd 1 ddrcke ddrba[1:0] ddrdqsx ddrdm[1:0] ddrdata[15:0] 2 dm2 1 ddrcmd contains ddrrasn, ddrcasn and ddrwen. (see chapter 7, ddr controller, in the rc32435 user reference manual ). ddrdqsx
22 of 53 january 19, 2006 idt 79rc32435 mdata[7:0] tsu_8c extclk rising 6.0 ? 6.0 ? 6.0 ? 6.0 ? ns see figures 8 and 9 (cont.). thld_8c 0 ? 0 ? 0 ? 0 ? ns tdo_8c 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5 ns tdz_8c 2 00.500.500.500.5ns tzd_8c 2 0.4 3.3 0.4 3.3 0.4 3.3 0.4 3.3 ns extclk 3 tper_8d none 7.5 ? 6.66 ? 6.66 ? 6.66 ? ns bdirn tdo_8e extclk rising 0.4 3.8 0.4 3.8 0.4 3.8 0.4 3.8 ns tdz_8e 2 ????????ns tzd_8e 2 ????????ns boen tdo_8f extclk rising 0.4 3.8 0.4 3.8 0.4 3.8 0.4 3.8 ns tdz_8f 2 ????????ns tzd_8f 2 ????????ns waitackn 4 tsu_8h extclk rising 6.5 ? 6.5 ? 6.5 ? 6.5 ? ns thld_8h 0?0?0?0?ns tpw_8h 2 none 2(extclk) ? 2(extclk) ? 2(extclk) ? 2(extclk) ?ns csn[3:0] tdo_8i extclk rising 0.4 4.0 0.4 4.0 0.4 4.0 0.4 4.0 ns tdz_8i 2 ????????ns tzd_8i 2 ????????ns rwn tdo_8j extclk rising 0.4 3.8 0.4 3.8 0.4 3.8 0.4 3.8 ns tdz_8j 2 ????????ns tzd_8j 2 ????????ns oen tdo_8k extclk rising 0.4 4.0 0.4 4.0 0.4 4.0 0.4 4.0 ns tdz_8k 2 ????????ns tzd_8k 2 ????????ns wen tdo_8l extclk rising 0.4 3.7 0.4 3.7 0.4 3.7 0.4 3.7 ns tdz_8l 2 ????????ns tzd_8l 2 ????????ns 1. the rc32435 provides bus turnaround cycles to prevent bus contention when going from read to write, write to read, and during e xternal bus ownership. for example, there are no cycles where an external device and the rc32435 are both driving. see chapter 6, device controller, in the rc32435 user referen ce manual. 2. the values for this symbol were determined by calculation, not by testing. 3. the frequency of extclk is programmable. see the external clock divider (mdata[5:4]) description in table 3 of this data sheet. 4. waitackn must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max table 8 memory and peripheral bus ac timing characteristics (part 2 of 2)
23 of 53 january 19, 2006 idt 79rc32435 figure 8 memory and peripheral bus ac timing waveform ? read access addr[21:0] addr[25:22] 1111 data tdo_8f tdo_8f tdo_8e tdo_8e tzd_8c tdz_8c tdo_8k tdo_8k tdo_8i tdo_8i tdo_8b tdo_8a thld_8c tsu_8c extclk maddr[21:0] maddr[25:22] rwn csn[3:0] wen oen mdata[7:0] bdirn boen waitackn rc32435 samples read data tper_8d thigh_8d tlow_8d
24 of 53 january 19, 2006 idt 79rc32435 figure 9 memory and peripheral bus ac timing waveform ? write access addr[21:0] addr[25:22] 1111 byte enables 1111 data tdo_8f tdo_8c tdo_8l tdo_8i tdo_8j tdo_8b tdo_8a extclk maddr[21:0] maddr[25:22] rwn csn[3:0] wen oen mdata[7:0] bdirn boen waitackn
25 of 53 january 19, 2006 idt 79rc32435 signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max ethernet miimdc tper_9a none 30.0 ? 30.0 ? 30.0 ? 30.0 ? ns see figure 10. thigh_9a, tlow_9a 12.0 ? 12.0 ? 12.0 ? 12.0 ? ns miimdio tsu_9b miimdc rising 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns thld_9b 0.0?0.0?0.0?0.0? ns tdo_9b 1 1. the values for this symbol were determined by calculation, not by testing. 10 300 10 300 10 300 10 300 ns ethernet ? mii mode miirxclk, miitxclk 2 2. the ethernet clock (miirxclk and miitxclk) frequency must be equal to or less than 1/2 iclk (miirxclk and miitxclk <= 1/2(iclk) ). tper_9c none 399.96 400.4 399.96 400.4 399.96 400.4 399.96 400.4 ns 10 mbps see figure 10. thigh_9c, tlow_9c 140 260 140 260 140 260 140 260 ns trise_9c, tfall_9c ?3.0?3.0?3.0?3.0ns miirxclk, miitxclk 2 tper_9d none 39.9 40.0 39.9 40.0 39.9 40.0 39.9 40.0 ns 100 mbps thigh_9d, tlow_9d 14.0 26.0 14.0 26.0 14.0 26.0 14.0 26.0 ns trise_9d, tfall_9d ?2.0?2.0?2.0?2.0ns miirxd[3:0], miirxdv, miirxer tsu_9e miixrxclk rising 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns thld_9e 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns miitxd[3:0], miitxenp, miitxer tdo_9f miixtxclk rising 0.0 25.0 0.0 25.0 0.0 25.0 0.0 25.0 ns ethernet ? rmii mode rmiirefclk tper_9i none 19.9 20.1 19.9 20.1 19.9 20.1 19.9 20.1 ns see figure 10. thigh_9i, tlow_9i 7.0 13.0 7.0 13.0 7.0 13.0 7.0 13.0 ns rmiitxen, rmiitxd[1:0] tdo_9j miirxclk rising 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns rmiicrsdv, rmiirxer, rmiirxd[1:0] tsu_9k 5.5 14.5 5.5 14.5 5.5 14.5 5.5 14.5 ns table 9 ethernet ac timing characteristics
26 of 53 january 19, 2006 idt 79rc32435 figure 10 ethernet ac timing waveform tdo_9b tdo_9b tdo_9f tdo_9f thld_9b tsu_9b tlow_9a thigh_9a tper_9a tlow_9d tlow thigh_9d tper_9d thld_9e tsu_9e tlow_9d tlow thigh_9d tper_9d miirxclk miirxdv, miirxd[3:0], miirxer miitxclk miitxen, miitxd[3:0], miitxer miimdc miimdio (output) miimdio (input) rmii refclk tper_9i thigh_9i tlow_9i tdo_9j tdo_9j rmii txen, rmii txd[1:0] rmii refclk tper_9i thigh_9i tlow_9i tsu_9k rmii crs_dv, rmii rxer rmii rxd[1:0]
27 of 53 january 19, 2006 idt 79rc32435 signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max pci 1 1. this pci interface conforms to the pci local bus specification, rev 2.2. pciclk 2 2. pciclk must be equal to or less than two times iclk (pciclk <= 2(iclk)) with a maximum pciclk of 66 mhz. tper_10a none 15.0 30.0 15.0 30.0 15.0 30.0 15.0 30.0 ns 66 mhz pci see figure 11. thigh_10a, tlow_10a 6.0 ? 6.0 ? 6.0 ? 6.0 ? ns tslew_10a 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 v/ns pciad[31:0], pciben[3:0], pcidevseln, pcifra- men,pciir- dyn, pcilockn, pcipar, pci- perrn, pcis- topn, pcitrdy tsu_10b pciclk rising 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns thld_10b 0 ? 0 ? 0 ? 0 ? ns tdo_10b 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns tdz_10b 3 3. the values for this symbol were determined by calculation, not by testing. ? 14.0 ? 14.0 ? 14.0 ? 14.0 ns tzd_10b 3 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns pcigntn[3:0], pcireqn[3:0] tsu_10c pciclk rising 5.0 ? 5.0 ? 5.0 ? 5.0 ? ns thld_10c 0 ? 0 ? 0 ? 0 ? ns tdo_10c 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns pcirstn (out- put) 4 4. pcirstn is an output in host mode and an input in satellite mode. tpw_10d 3 none 4000 (clk) ? 4000 (clk) ? 4000 (clk) ? 4000 (clk) ? ns see figures 15 and 16 pcirstn (input) 4,5 5. to meet the pci delay specification from reset asserted to outputs floating, the pci reset should be logically combined with th e coldrstn input, instead of input on pcirstn. tpw_10e 3 none 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ? ns tdz_10e 3 pcirstn falling 6(clk) ? 6(clk) ? 6(clk) ? 6(clk) ? ns pciserrn 6 6. pciserrn and pcimuintn use open collector i/o types. tsu_10f pciclk rising 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns see figure 11 thld_10f 0 ? 0 ? 0 ? 0 ? ns tdo_10f 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns pcimuintn 6 tdo_10g pciclk rising 4.7 11.1 4.7 11.1 4.7 11.1 4.7 11.1 ns table 10 pci ac timing characteristics
28 of 53 january 19, 2006 idt 79rc32435 figure 11 pci ac timing waveform figure 12 pci ac timing waveform ? pci reset in host mode tdo_10c tzd_10b tdz_10b tdo_10b thld_10c tsu_10c thld_10b tsu_10b thigh_10a tper_10a tper_10a valid valid pciclk bussed output point to point output bussed input point to point input tlow_10a tpw_10d tpw_10d pci interface enabled cold reset warm reset coldrstn pcirstn (output) rstn note: during and after cold reset, pcirstn is tri-stated and requires a pull-down to reach a low state. after the pci interface is enabled in host mode, pcirstn will be driven either high or low depending on the (tri-state) reset state of the rc32435.
29 of 53 january 19, 2006 idt 79rc32435 figure 13 pci ac timing waveform ? pci reset in satellite mode signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit conditions timing diagram reference min max min max min max min max i 2 c 1 scl frequency none 0 100 0 100 0 100 0 100 khz 100 khz see figure 14. thigh_12a, tlow_12a 4.0 ? 4.0 ? 4.0 ? 4.0 ? s trise_12a ? 1000 ? 1000 ? 1000 ? 1000 ns tfall_12a ? 300 ? 300 ? 300 ? 300 ns sda tsu_12b scl rising 250 ? 250 ? 250 ? 250 ? ns thld_12b 0 3.45 0 3.45 0 3.45 0 3.45 s trise_12b ? 1000 ? 1000 ? 1000 ? 1000 ns tfall_12b ? 300 ? 300 ? 300 ? 300 ns start or repeated start condition tsu_12c sda falling 4.7 ? 4.7 ? 4.7 ? 4.7 ? s thld_12c 4.0 ? 4.0 ? 4.0 ? 4.0 ? s stop condition tsu_12d sda rising 4.0 ? 4.0 ? 4.0 ? 4.0 ? s bus free time between a stop and start condi- tion tdelay_12e 4.7 ? 4.7 ? 4.7 ? 4.7 ? s scl frequency none 0 400 0 400 0 400 0 400 khz 400 khz thigh_12a, tlow_12a 0.6 ? 0.6 ? 0.6 ? 0.6 ? s trise_12a ? 300 ? 300 ? 300 ? 300 ns tfall_12a ? 300 ? 300 ? 300 ? 300 ns sda tsu_12b scl rising 100 ? 100 ? 100 ? 100 ? ns thld_12b 0 0.9 0 0.9 0 0.9 0 0.9 s trise_12b ? 300 ? 300 ? 300 ? 300 ns tfall_12ba ? 300 ? 300 ? 300 ? 300 ns table 11 i 2 c ac timing characteristics (part 1 of 2) tdz_10e tpw_10e tpw_10e warm reset clkp pcirstn (input) rstn mdata[15:0] pci bus signals
30 of 53 january 19, 2006 idt 79rc32435 figure 14 i2c ac timing waveform figure 15 gpio ac timing waveform start or repeated start condition tsu_12c sda falling 0.6 ? 0.6 ? 0.6 ? 0.6 ? s 400 khz see figure 14. thld_12c 0.6 ? 0.6 ? 0.6 ? 0.6 ? s stop condition tsu_12d sda rising 0.6 ? 0.6 ? 0.6 ? 0.6 ? s bus free time between a stop and start condi- tion tdelay_12e 1.3 ? 1.3 ? 1.3 ? 1.3 ? s 1. for more information, see the i 2 c-bus specification by philips semiconductor. signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max gpio gpio[13:0] tpw_13b 1 1. the values for this symbol were determined by calculation, not by testing. none 2(iclk) ? 2(iclk) ? 2(iclk) ? 2(iclk) ? ns see figure 15. table 12 gpio ac timing characteristics signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit conditions timing diagram reference min max min max min max min max table 11 i 2 c ac timing characteristics (part 2 of 2) tsu_12d thld_12c tsu_12c tsu_12b thld_12b thigh_12a thld_12c tlow_12a sda scl tdelay_12e gpio (asynchronous input) tpw_13b
31 of 53 january 19, 2006 idt 79rc32435 figure 16 spi ac timing waveform ? clock polarity 0, clock phase 0 figure 17 spi ac timing waveform ? clock polarity 0, clock phase 1 signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max spi 1 1. in spi mode, the sck period and sampling edge are programmable. in pci mode, the sck period is fixed and the sampling edge is r ising. sck tper_15a none 100 166667 100 166667 100 166667 100 166667 ns spi see figures 16, 17, and 18. thigh_15a, tlow_15a 40 83353 40 83353 40 83353 40 83353 ns spi sdi tsu_15b sck rising or falling 60 ? 60 ? 60 ? 60 ? ns spi see figures 16, 17, and 18. thld_15b 60 ? 60 ? 60 ? 60 ? ns spi sdo tdo_15c sck rising or falling 060060060060ns spi sck, sdi, sdo tpw_15e none 2(iclk) ? 2(iclk) ? 2(iclk) ? 2(iclk) ?nsbit i/o table 13 spi ac timing characteristics tdo_15c thld_15b tsu_15b tlow_15a thigh_15a tper_15a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 0 in the spi control register, spc. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck sdi sdo tdo_15c thld_15b tsu_15b tlow_15a thigh_15a tper_15a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 1 in the spi control register, spc. msb bit 6 bit 4 bit 5 bit 3 bit 1 bit 2 lsb sck sdi sdo
32 of 53 january 19, 2006 idt 79rc32435 figure 18 spi ac timing waveform ? bit i/o mode signal symbol reference edge 266mhz 300mhz 350mhz 400mhz unit condi- tions timing diagram reference min max min max min max min max ejtag and jtag jtag_tck tper_16a none 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0 ns see figure 19. thigh_16a, tlow_16a 10.0 25.0 10.0 25.0 10.0 25.0 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that both jtag_tms and ejtag_tms should be held at 1 while the signal applied a t jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag_tck when either jtag _tms or ejtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset state. tsu_16b jtag_tck rising 2.4 ? 2.4 ? 2.4 ? 2.4 ? ns thld_16b 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns jtag_tdo tdo_16c jtag_tck fall- ing ? 11.3 ? 11.3 ? 11.3 ? 11.3 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ? 11.3 ? 11.3 ? 11.3 ? 11.3 ns jtag_trst_ n tpw_16d 2 none 25.0 ? 25.0 ? 25.0 ? 25.0 ? ns ejtag_tms 1 tsu_16e jtag_tck rising 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns thld_6e 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns table 14 jtag ac timing characteristics sck, sdi, sdo (input) tpw_15e
33 of 53 january 19, 2006 idt 79rc32435 figure 19 jtag ac timing waveform the ieee 1149.1 specification requires that the jtag and ejtag tap controllers be reset at power-up whether or not the interfac es are used for a boundary scan or a probe. reset can occur through a pull-down resistor on jtag_trst_n if the probe is not connected. however, on-chip pull-up resistors are implemented on the rc32435 due to an ieee 1149.1 requirement. having on-chip pull-up and external pull-down resis tors for the jtag_trst_n signal requires special care in the design to ensure that a valid logical level is provided to jtag_trst_n, such as using a small external pull-down resistor to ensure this level overrides the on-chip pull-up. an alternative is to use an active power-up res et circuit for jtag_trst_n, which drives jtag_trst_n low only at power-up and then holds jtag_trst_n high afterwards with a pull-up resistor. figure 20 shows the electrical connection of the ejtag probe target system connector. figure 20 target system electrical ejtag connection tpw_16d tpw_16d tdz_16c tdo_16c thld_16e tsu_16e thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms ejtag_tms jtag_tdo jtag_trst_n gnd 1 gnd gnd gnd gnd trst* tdi tdo tms tck rst* dint jtag_trst_n jtag_tdi jtag_tdo ejtag_tms jtag_tck gnd vdd gnd vccio voltage reference pull-up pull-down series-res. reset (soft/hard) target system reset circuit pull-up other reset sources vccio rc32435 no connect
34 of 53 january 19, 2006 idt 79rc32435 using the ejtag probe using the ejtag probe using the ejtag probe using the ejtag probe in figure 20, the pull-up resistors for jtag_tdo and rst*, the pull-down resistor for jtag_trst_n, and the series resistor for jtag_tdo must be adjusted to the specific design. however, the recommended pull-up/down resistor is 1.0 k ? because a low value reduces crosstalk on the cable to the connector, allowing higher jtag_tck frequencies. a typical value for the series resistor is 33 ? . recommended resistor values have 5% toler- ance. if a probe is used, the pull-up resistor on jtag_tdo must ensure that the jtag_tdo level is high when no probe is connected and the jtag_tdo output is tri-stated. this requirement allows reliable connection of the probe if it is hooked-up when the power is al ready on (hot plug). the pull-up resistor value of around 47 k ? should be sufficient. optional diodes to protect against overshoot and undershoot voltage can be added on the signals of the chip with ejtag. if a probe is used, the rst* signal must have a pull-up resistor because it is controlled by an open-collector (oc) driver in t he probe, and thus is actively pulled low only. the pull-up resistor is responsible for the high value when not driven by the probe of 25pf. the inpu t on the target system reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. v cc i/o must connect to a voltage reference that drops rapidly to below 0.5v when the target system loses power, even with a capacitive load of 25pf. the probe can thus detect the lost power condition. for additional information on ejtag, refer to chapter 17 of the rc32435 user reference manual. p p p phase-locked loop (pll) hase-locked loop (pll) hase-locked loop (pll) hase-locked loop (pll) the phase-locked loop (pll) multiplies the external oscillator input (pin clk) according to the parameter provided by the boot configuration vector to create the processor clock (pclk). inherently, pll circuits are only capable of generating clock frequencies within a limite d range. pll filters it is recommended that the system designer provide a filter network of passive components for the pll analog and digital power supplies. the pll circuit power and pll circuit ground should be isolated from power and ground with a filter circuit such as the one shown in fi gure 21. because the optimum values for the filter components depend upon the application and the system noise environment, these values should be c onsidered as starting points for further experimentation within your specific application. figure 21 pll filter circuit for noisy environments 10 f0.1 f 100 pf v cc v ss v cc pll v ss pll 10 ohm 1 rc32435 v cc pll v ss pll
35 of 53 january 19, 2006 idt 79rc32435 recommended operating supply voltages recommended operating supply voltages recommended operating supply voltages recommended operating supply voltages recommended operating temperatures recommended operating temperatures recommended operating temperatures recommended operating temperatures capacitive load deration capacitive load deration capacitive load deration capacitive load deration refer to the 79 rc 32435 i bis model on the idt web site (www.idt.com). symbol parameter minimum typical maximum unit v ss common ground 0 0 0 v v ss pll pll ground v cc i/o i/o supply except for sstl_2 1 1. sstl_2 i/os are used to connect to ddr sdram. 3.135 3.3 3.465 v v cc si/o (ddr) i/o supply for sstl_2 1 2.375 2.5 2.625 v v cc pll pll supply (digital) 1.1 1.2 1.3 v v cc apll pll supply (analog) 3.135 3.3 3.465 v v cc core internal logic supply 1.1 1.2 1.3 v ddrvref 2 2. peak-to-peak ac noise on ddrvref may not exceed 2% ddrvref (dc). sstl_2 input reference voltage 0.5(vccsi/o) 0.5(vccsi/o) 0.5(vccsi/o) v v tt 3 3. v tt of the sstl_2 transmitting device must track ddrvref of the receiving device. sstl_2 termination voltage ddrvref - 0.04 ddrvref ddrvref + 0.04 v table 15 rc32435 operating voltages grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 16 rc32435 operating temperatures
36 of 53 january 19, 2006 idt 79rc32435 power-on power-on power-on power-on sequence sequence sequence sequence three power-on sequences are given below. sequence #1 is recommended because it will prevent i/o conflicts and will also allow the input signals to propagate when the i/o powers are brought up. note: the esd diodes may be damaged if one of the voltages is applied and one of the other voltages is at a ground level. a . recommended sequence t2 > 0 whenever possible (v cc core) t1 - t2 can be 0 (v cc si/o followed by v cc i/o) b . reverse voltage sequence if sequence a is not feasible, then sequence b can be used: t1 <50ms and t2 <50ms to prevent damage. c . simultaneous power-up vcci/o, vccsi/o, and vcccore can be powered up simultaneously. 1.2v 3.3v 2.5v time t1 t2 v cc i/o v cc si/o v cc core vcci/o -- 3.3v vccsi/o -- 2.5v vcccore -- 1.2v vcc1.2 vcc3.3 vcc2.5 time t1 t2 vcci/o -- 3.3v vccsi/o -- 2.5v vcccore -- 1.2v vcccore vccsi/o vcci/o
37 of 53 january 19, 2006 idt 79rc32435 p p p power consumptio ower consumptio ower consumptio ower consumption n n n power curve power curve power curve power curve the following graph contains a power curve that shows power consumption at various core frequencies. figure 22 rc32435 typical power usage parameter 266mhz 300mhz 350mhz 400mhz unit conditions typ. max. typ. max. typ. max. typ. max. i cc i/o 215 270 220 275 225 280 230 285 ma c l = 35 pf t ambient = 25 o c max. values use the maximum volt- ages listed in table 15. typical val- ues use the typical voltages listed in that table. note: for additional information, see p ower considerations for idt processors on the idt web site www.idt.com. i cc si/o (ddr) 708575908510095110ma i cc core, i cc pll normal mode 325 510 350 550 400 610 450 670 ma standby mode 1 1. the rc32435 enter standby mode by executing wait instructions. minimal i/o switching is assumed. on-chip logic outside the cpu core continues to function. 220 ? 240 ? 260 ? 280 ? ma power dissipation normal mode 1.27 1.82 1.36 1.90 1.45 2.02 1.54 2.15 w standby mode 1 0.73 ? 0.78 ? 0.84 ? 0.90 ? w table 17 rc32435 power consumption typical power curve 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 266 300 350 400 core frequency (mhz) power (w)
38 of 53 january 19, 2006 idt 79rc32435 dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 15. note: see table 2, pin characteristics, for a complete i/o listing. note 1: i oh (ac) max = (98/v cc i/o) * (v out - v cc i/o) * (v out + 0.4v cc i/o) note 2: i ol (ac) max = (256/v cc i/o) * v out * (v cc i/o - v out ) i/o type para- meter min. typical max. unit conditions low drive output i ol ? 14.0 ? ma v ol = 0.4v i oh ? -12.0 ? ma v oh = 1.5v high drive output i ol ? 41.0 ? ma v ol = 0.4v i oh ? -42.0 ? ma v oh = 1.5v schmitt trigger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v cc i/o + 0.5 v? sstl_2 (for ddr sdram) i ol 7.6 ? ? ma v ol = 0.5v i oh -7.6 ? ? ma v oh = 1.76v v il -0.3 ? 0.5(v cc si/o) - 0.18 v v ih 0.5(v cc si/o) + 0.18 ? v cc si/o + 0.3 v pci i oh (ac) switching -12(v cc i/o) ? ?ma0 < v out < 0.3(v cc i/o) -17.1(v cc i/o - v out ) ? ?ma0.3(v cc i/o) < v out < 0.9(v cc i/o) ?? -32(v cc i/o) ? 0.7(v cc i/o) 16(v cc i/o) ? see note 1 ma 0.7(v cc i/o) < v out < v cc i/o i ol (ac) switching +16(v cc i/o) ? ?mav cc i/o > v out > 0.6(v cc i/o) +26.7(v out ) ? ?ma 0.6(v cc i/o) > v out > 0.1(v cc i/o) ? ? +38(v cc i/o) ma v out = 0.18(v cc i/o) ? ? see note 2 ma 0.18(v cc i/o) > v out > 0 v il -0.3 ? 0.3(v cc i/o) v v ih 0.5(v cc i/o) ? 5.5 v capacitance c in ? ? 10.5 pf ? leakage inputs ??+ 10 a vcc (max) i/o leak w / o pull-ups/ downs ??+ 10 a vcc (max) i/o leak with pull-ups/ downs ??+ 80 a vcc (max) table 18 dc electrical characteristics
39 of 53 january 19, 2006 idt 79rc32435 ac test conditions ac test conditions ac test conditions ac test conditions figure 23 ac test conditions input reference voltage parameter value units sstl i/o other i/o input pulse levels 0 to 2.5 0 to 3.3 v input rise/fall 0.8 1.0 ns input reference level 0.5(vccsi/o) 0.5(vcci/o) v output reference levels 1.25 1.5 v ac test load 35 35 pf rc32435 output . 50 ? 50 ? test point
40 of 53 january 19, 2006 idt 79rc32435 absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings symbol parameter min 1 1. functional and tested operating conditions are given in table 15. absolute maximum ratings are stress ratings only, and func- tional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause perma- nent damage to the device. max 1 unit v cc i/o i/o supply except for sstl_2 2 2. sstl_2 i/os are used to connect to ddr sdram. -0.6 4.0 v v cc si/o (ddr) i/o supply for sstl_2 2 -0.6 4.0 v v cc core core supply voltage -0.6 2.0 v v cc pll pll supply (digital) -0.6 2.0 v v cc apll pll supply (analog) -0.6 4.0 v vini/o i/o input voltage except for sstl_2 -0.6 v cc i/o+ 0.5 v vinsi/o i/o input voltage for sstl_2 -0.6 v cc si/o+ 0.5 v t a industrial ambient operating temperature -40 +85 c t a commercial ambient operating temperature 0 +70 c t s storage temperature -40 +125 c table 19 absolute maximum ratings
41 of 53 january 19, 2006 idt 79rc32435 p p p package pin-out ? ackage pin-out ? ackage pin-out ? ackage pin-out ? 256-bga s 256-bga s 256-bga s 256-bga signal pinout for ignal pinout for ignal pinout for ignal pinout for the rc the rc the rc the rc32435 32435 32435 32435 the following table lists the pin numbers, signal names, and number of alternate functions for the rc32435 device. signal names ending with an ?_n? or ?n? are active when low. pin function alt pin function alt pin function alt pin function alt a1 rwn e1 miirxd[3] j1 gpio[3] 1 n1 pciad[29] a2 oen e2 miirxd[2] j2 jtag_tck n2 pciad[28] a3 csn[2] e3 miitxd[0] j3 gpio[2] 1 n3 pciad[30] a4 csn[0] e4 miitxd[1] j4 ejtag_tms n4 pciad[18] a5 maddr[10] e5 v cc i/0 j5 v cc core n5 pcireqn[1] a6 mdata[6] e6 v cc i/0 j6 v ss n6 pcireqn[2] a7 gpio[7] 1 e7 v cc i/0 j7 v ss n7 pciirdyn a8 gpio[4] 1 e8 v cc core j8 v ss n8 pcilockn a9 maddr[16] e9 v cc core j9 v ss n9 pciperrn a10 maddr[13] e10 v cc i/0 j10 v ss n10 pciad[15] a11 v ss pll e11 v cc ddr j11 v cc core n11 pciad[11] a12 jtag_tdi e12 v cc ddr j12 v cc core n12 pcicben[0] a13 maddr[9] e13 ddrdata[6] j13 ddrckn n13 ddraddr[5] a14 maddr[7] e14 ddrdata[5] j14 ddrvref n14 ddraddr[4] a15 maddr[5] e15 ddraddr[13] j15 ddrckp n15 ddraddr[3] a16 maddr[2] e16 ddrdata[4] j16 ddrdqs[0] n16 ddrba[0] b1 boen f1 miitxd[2] k1 jtg_tdo p1 pciad[27] b2 rstn f2 miirxclk k2 sck p2 pciad[26] b3 csn[3] f3 miitxd[3] k3 reserved p3 gpio[10] 1 b4 csn[1] f4 miitxenp k4 sdo p4 pciad[20] b5 maddr[11] f5 v cc i/0 k5 v cc i/0 p5 pcireqn[3] b6 mdata[1] f6 v ss k6 v cc i/0 p6 pcireqn[0] b7 mdata[4] f7 v ss k7 v ss p7 pciframen b8 gpio[5] 1 f8 v ss k8 v ss p8 pcistopn b9 maddr[17] f9 v cc core k9 v ss p9 pciserrn b10 maddr[12] f10 v ss k10 v ss p10 pciad[14] b11 v cc pll f11 v ss k11 v ss p11 pciad[10] b12 v ss apll f12 v cc ddr k12 v cc ddr p12 pciad[7] b13 maddr[8] f13 ddrdata[9] k13 ddrcke p13 pciad[4] b14 maddr[6] f14 ddrdata[8] k14 ddraddr[11] p14 ddraddr[0] b15 maddr[3] f15 ddrdm[0] k15 ddraddr[10] p15 ddraddr[2] b16 maddr[1] f16 ddrdata[7] k16 ddraddr[12] p16 ddrcsn c1 extclk g1 miirxdv l1 sda r1 pciad[25] table 20 rc32435 pinout (part 1 of 2)
42 of 53 january 19, 2006 idt 79rc32435 c2 bdirn g2 miitxer l2 scl r2 pcicben[3] c3 coldrstn g3 miirxer l3 gpio[8] 1 r3 pciad[23] c4 wen g4 miitxclk l4 sdi r4 pciad[21] c5 mdata[3] g5 v cc i/0 l5 v cc i/0 r5 pciad[17] c6 mdata[5] g6 v ss l6 v ss r6 pcirstn c7 gpio[6] 1 g7 v ss l7 v ss r7 pcicben[2] c8 maddr[21] g8 v ss l8 v cc core r8 pcitrdyn c9 maddr[18] g9 v ss l9 v ss r9 pcicben[1] c10 maddr[14] g10 v ss l10 v ss r10 pciad[12] c11 jtag_tms g11 v ss l11 v ss r11 pciad[8] c12 v cc apll g12 v cc ddr l12 v cc ddr r12 pciad[5] c13 clk g13 ddrdm[1] l13 ddraddr[9] r13 pciad[3] c14 maddr[4] g14 ddrdqs[1] l14 ddrwen r14 pciad[0] c15 maddr[0] g15 ddrdata[10] l15 ddrcasn r15 pcigntn[2] c16 ddrdata[0] g16 ddrdata[11] l16 ddraddr[8] r16 ddraddr[1] d1 miirxd[0] h1 miimdio m1 gpio[12] 1 t1 pciad[24] d2 miicl h2 miimdc m2 pciad[31] t2 gpio[13] 1 d3 miicrs h3 gpio[0] 1 m3 gpio[11] 1 t3 pciad[22] d4 miirxd[1] h4 gpio[1] 1 m4 gpio[9] 1 t4 pciad[19] d5 mdata[7] h5 v cc core m5 v cc i/0 t5 pciad[16] d6 mdata[2] h6 v cc core m6 v cc i/0 t6 pciclk d7 mdata[0] h7 v ss m7 v cc i/0 t7 pcigntn[0] d8 maddr[20] h8 v ss m8 v cc core t8 pcidevseln d9 maddr[19] h9 v ss m9 v cc core t9 pcipar d10 maddr[15] h10 v ss m10 v cc i/0 t10 pciad[13] d11 extbcv h11 v ss m11 v cc ddr t11 pciad[9] d12 jtag_trstn h12 v cc core m12 v cc ddr t12 pciad[6] d13 waitackn h13 ddrdata[15] m13 ddrrasn t13 pciad[2] d14 ddrdata[2] h14 ddrdata[14] m14 ddrba[1] t14 pciad[1] d15 ddrdata[3] h15 ddrdata[12] m15 ddraddr[6] t15 pcigntn[1] d16 ddrdata[1] h16 ddrdata[13] m16 ddraddr[7] t16 pcigntn[3] pin function alt pin function alt pin function alt pin function alt table 20 rc32435 pinout (part 2 of 2)
43 of 53 january 19, 2006 idt 79rc32435 rc rc rc rc32435 a 32435 a 32435 a 32435 alternate signal functions lternate signal functions lternate signal functions lternate signal functions rc rc rc rc32435 p 32435 p 32435 p 32435 power pins ower pins ower pins ower pins pin gpio alternate pin gpio alternate a7 gpio[7] maddr[25] j3 gpio[2] u0rtsn a8 gpio[4] maddr[22] l3 gpio[8] cpu b8 gpio[5] maddr[23] m1 gpio[12] pcigntn[5] c7 gpio[6] maddr[24] m3 gpio[11] pcireqn[5] h3 gpio[0] u0sout m4 gpio[9] pcireqn[4] h4 gpio[1] u0sinp p3 gpio[10] pcigntn[4] j1 gpio[3] u0ctsn t2 gpio[13] pcimuintn table 21 rc32435 alternate signal functions v cc i/o v cc ddr v cc core v cc pll v cc apll e5 e11 e8 b11 c12 e6 e12 e9 e7 f12 f9 e10 g12 h5 f5 k12 h6 g5 l12 h12 k5 m11 j5 k6 m12 j11 l5 j12 m5 l8 m6 m8 m7 m9 m10 table 22 rc32435 power pins
44 of 53 january 19, 2006 idt 79rc32435 rc rc rc rc32435 g 32435 g 32435 g 32435 ground pins round pins round pins round pins r r r rc c c c32435 s 32435 s 32435 s 32435 signals listed alphabetically ignals listed alphabetically ignals listed alphabetically ignals listed alphabetically the following table lists the rc32435 pins in alphabetical order. v ss v ss v ss pll f6 j6 a11, b12 f7 j7 f8 j8 f10 j9 f11 j10 g6 k7 g7 k8 g8 k9 g9 k10 g10 k11 g11 l6 h7 l7 h8 l9 h9 l10 h10 l11 h11 table 23 rc32435 ground pins signal name i/o type location signal category bdirn o c2 memory and peripheral bus boen o b1 clk i c13 system coldrstn i c3 csn[0] o a4 memory and peripheral bus csn[1] o b4 csn[2] o a3 csn[3] o b3 table 24 rc32435 alphabetical signal list (part 1 of 7)
45 of 53 january 19, 2006 idt 79rc32435 ddraddr[0] o p14 ddr bus ddraddr[1] o r16 ddraddr[2] o p15 ddraddr[3] o n15 ddraddr[4] o n14 ddraddr[5] o n13 ddraddr[6] o m15 ddraddr[7] o m16 ddraddr[8] o l16 ddraddr[9] o l13 ddraddr[10] o k15 ddraddr[11] o k14 ddraddr[12] o k16 ddraddr[13] o e15 ddrba[0] o n16 ddrba[1] o m14 ddrcasn o l15 ddrcke o k13 ddrckn o j13 ddrckp o j15 ddrcsn o p16 ddrdata[0] i/o c16 ddrdata[1] i/o d16 ddrdata[2] i/o d14 ddrdata[3] i/o d15 ddrdata[4] i/o e16 ddrdata[5] i/o e14 ddrdata[6] i/o e13 ddrdata[7] i/o f16 ddrdata[8] i/o f14 ddrdata[9] i/o f13 ddrdata[10] i/o g15 ddrdata[11] i/o g16 ddrdata[12] i/o h15 ddrdata[13] i/o h16 ddrdata[14] i/o h14 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 2 of 7)
46 of 53 january 19, 2006 idt 79rc32435 ddrdata[15] i/o h13 ddr bus ddrdm[0] o f15 ddrdm[1] o g13 ddrdqs[0] i/o j16 ddrdqs[1] i/o g14 ddrrasn o m13 ddrvref i j14 ddrwen o l14 ejtag_tms i j4 jtag / ejtag extbcv i d11 system extclk o c1 gpio[0] i/o h3 general purpose input/output gpio[1] i/o h4 gpio[2] i/o j3 gpio[3] i/o j1 gpio[4] i/o a8 gpio[5] i/o b8 gpio[6] i/o c7 gpio[7] i/o a7 gpio[8] i/o l3 gpio[9] i/o m4 gpio[10] i/o p3 gpio[11] i/o m3 gpio[12] i/o m1 gpio[13] i/o t2 jtag_tck i j2 jtag / ejtag jtag_tdi i a12 jtag_tdo o k1 jtag_tms i c11 jtag_trstn i d12 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 3 of 7)
47 of 53 january 19, 2006 idt 79rc32435 maddr[0] o c15 memory and peripheral bus maddr[1] o b16 maddr[2] o a16 maddr[3] o b15 maddr[4] o c14 maddr[5] o a15 maddr[6] o b14 maddr[7] o a14 maddr[8] o b13 maddr[9] o a13 maddr[10] o a5 maddr[11] o b5 maddr[12] o b10 maddr[13] o a10 maddr[14] o c10 maddr[15] o d10 maddr[16] o a9 maddr[17] o b9 maddr[18] o c9 maddr[19] o d9 maddr[20] o d8 maddr[21] o c8 mdata[0] i/o d7 mdata[1] i/o b6 mdata[2] i/o d6 mdata[3] i/o c5 mdata[4] i/o b7 mdata[5] i/o c6 mdata[6] i/o a6 mdata[7] i/o d5 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 4 of 7)
48 of 53 january 19, 2006 idt 79rc32435 miicl i d2 ethernet interface miicrs i d3 miimdc o h2 miimdio i/o h1 miirxclk i f2 miirxd[0] i d1 miirxd[1] i d4 miirxd[2] i e2 miirxd[3] i e1 miirxdv i g1 miirxer i g3 miitxclk i g4 miitxd[0] o e3 miitxd[1] o e4 miitxd[2] o f1 miitxd[3] o f3 miitxenp o f4 miitxer o g2 oen o a2 memory and peripheral bus pciad[0] i/o r14 pci bus interface pciad[1] i/o t14 pciad[2] i/o t13 pciad[3] i/o r13 pciad[4] i/o p13 pciad[5] i/o r12 pciad[6] i/o t12 pciad[7] i/o p12 pciad[8] i/o r11 pciad[9] i/o t11 pciad[10] i/o p11 pciad[11] i/o n11 pciad[12] i/o r10 pciad[13] i/o t10 pciad[14] i/o p10 pciad[15] i/o n10 pciad[16] i/o t5 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 5 of 7)
49 of 53 january 19, 2006 idt 79rc32435 pciad[17] i/o r5 pci bus interface pciad[18] i/o n4 pciad[19] i/o t4 pciad[20] i/o p4 pciad[21] i/o r4 pciad[22] i/o t3 pciad[23] i/o r3 pciad[24] i/o t1 pciad[25] i/o r1 pciad[26] i/o p2 pciad[27] i/o p1 pciad[28] i/o n2 pciad[29] i/o n1 pciad[30] i/o n3 pciad[31] i/o m2 pciben[0] i/o n12 pciben[1] i/o r9 pciben[2] i/o r7 pciben[3] i/o r2 pciclk i t6 pcidevseln i/o t8 pciframen i/o p7 pcigntn[0] i/o t7 pcigntn[1] i/o t15 pcigntn[2] i/o r15 pcigntn[3] i/o t16 pciirdyn i/o n7 pcilockn i/o n8 pcipar i/o t9 pciperrn i/o n9 pcireqn[0] i/o p6 pcireqn[1] i/o n5 pcireqn[2] i/o n6 pcireqn[3] i/o p5 pcirstn i/o r6 pciserrn i/o p9 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 6 of 7)
50 of 53 january 19, 2006 idt 79rc32435 pcistopn i/o p8 pci bus interface pcitrdyn i/o r8 rstn i/o b2 system rwn o a1 memory and peripheral bus sck i/o k2 serial peripheral interface scl i/o l2 i 2 c sda i/o l1 sdi i/o l4 serial peripheral interface sdo i/o k4 vcc apll c12 power vcc core e8, e9, f9, h5, h6, h12, j5, j11, j12, l8, m8, m9 vcc ddr e11, e12, f12, g12, k12, l12, m11, m12 vcc i/o e5, e6, e7, e10, f5, g5, k5, k6, l5, m5, m6, m7, m10 vcc pll b11 vss f6, f7, f8, f10, f11, g6, g7, g8, g9, g10, g11, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, k7, k8, k9, k10, k11, l6, l7, l9, l10, l11 ground vss apll b12 vss pll a11 waitackn i d13 memory and peripheral bus wen o c4 reserved k3, l1, l2 signal name i/o type location signal category table 24 rc32435 alphabetical signal list (part 7 of 7)
51 of 53 january 19, 2006 idt 79rc32435 r r r rc c c c32435 p 32435 p 32435 p 32435 package drawing ? ackage drawing ? ackage drawing ? ackage drawing ? 256-pin 256-pin 256-pin 256-pin ca ca ca cabga bga bga bga
52 of 53 january 19, 2006 idt 79rc32435 rc rc rc rc32435 p 32435 p 32435 p 32435 package drawing ackage drawing ackage drawing ackage drawing ? ? ? ? page two page two page two page two
53 of 53 january 19, 2006 idt 79rc32435 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: rischelp@idt.com phone: 408-284-8208 ordering information ordering information ordering information ordering information valid combinations valid combinations valid combinations valid combinations 79rc32h435 - 266bc, 300bc, 350bc, 400bc 256-pin cabga package, commercial temperature 79rc32h435 - 266bci, 300bci, 350bci 256-pin cabga package, industrial temperature 79rcxx yy xxxx 999 a a operating voltage device type speed package temp range/ process h blank commercial temperature (0c to +70c ambient) integrated core processor product type 79rc32 32-bit embedded microprocessor 256-pin cabga bc 266 266 mhz pipeline clk 435 i industrial temperature (-40 c to +85 c ambient) 300 300 mhz pipeline clk 1.2v +/- 0.1v core voltage 350 350 mhz pipeline clk 400 mhz pipeline clk 400

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